1. Field of the Invention
The present invention relates to a non-volatile memory device. More particularly, the present invention relates to a non-volatile memory with non-volatile memory cell having asymmetrical doped structure and method of operating the memory cell.
2. Description of the Related Art
Electrically erasable programmable read only memory (EEPROM) is a type of non-volatile memory that allows multiple data writing, reading and erasing operations. The stored data will be retained even after power to the device is removed. With these advantages, EEPROM become one of the most widely adopted non-volatile memories for personal computer and electronic equipment.
A typical EEPROM has a floating gate and a control gate fabricated using doped polysilicon. To program data into the memory, electrons injected into the floating gate are distributed evenly within the polysilicon floating gate layer. Obviously, if there are some defects in the tunneling oxide layer underneath the polysilicon floating gate layer, the device may leak and lead to a drop in reliability.
At present, a type of flash memory cell that programs through hot-hole injection nitride electron storage (PHINES) has been developed as shown in FIG. 1.
FIG. 1 is a schematic cross-sectional view of a conventional programming through hot-hole injection nitride electron storage (PHINES) type flash memory cell. As shown in FIG. 1, the flash memory cell 10 typically comprises a substrate 100, a control gate 120 over the substrate 100, a source 130a and a drain 130b within the substrate 100 and an oxide/nitride/oxide (ONO) layer 110 between the control gate 120 and the substrate 100. The oxide/nitride/oxide (ONO) layer 110 comprises two silicon oxide layers 112 and 116 and a silicon nitride layer 114 sandwiched between them. In general, the silicon nitride layer 114 serves as a charge-trapping layer therein.
The PHINES type flash memory cell in FIG. 1 utilizes band-to-band tunneling hot-hole (BTBTHH) to program data and utilizes the uniform Fowler-Nordheim (FN) channel to erase data.
Although the advantages of PHINES type flash memory cell includes low power consumption, a low leakage current and a simplified manufacturing method, some unavoidable defects are still present. For example, a PHINES type flash memory cell is designed to store a bit of data near the drain region and another bit of data near the source region. However, if the drain region has already stored up a single data bit, the second bit effect is produced when a reverse reading operation is carried out. The second bit effect often leads to a drop in the threshold voltage (Vt) in reverse reading and hence requires a higher bias voltage for reading. Yet, with a high read-out bias voltage, read-out interference will be intensified. Furthermore, the PHINES type flash memory cell has a relatively slow programming speed. In addition, a typical PHINES flash memory cell needs to incorporate three sets of bit line selection transistors (BLT) for programming. Hence, the overhead area for accommodating the bit line selection transistors is large and the actual packing density of the memory cell array is reduced.